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irfr9310, irfu9310, sihfr9310, sihfu9310 www.vishay.com vishay siliconix s13-0166-rev. d, 04-feb-13 1 document number: 91284 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 power mosfet features ?p-channel ? surface mount (irfr9310, sihfr9310) ? straight lead (irfu9310, sihfu9310) ? advanced process technology ? fast switching ? fully avalanche rated ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 description third generation power mosf ets from vishay utilize advanced processing techniques to achieve low on-resistance per silicon area. this benefit, combined with the fast switching speed and ru ggedized device design that power mosfets are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. the dpak is designed for surface mountin g using vapor phase, infrared, or wave soldering techniques. the straight lead version (irfu/sihfu series) is for through-hole mounting applications. power dissipation levels up to 1.5 w are possible in typical surface mount applications. note a. see device orientation. notes a. repetitive rating; pu lse width limited by maximum junction temperature (see fig. 11). b. starting t j = 25 c, l = 57 mh, r g = 25 ? , i as = - 1.8 a (see fig. 12). c. i sd ? - 1.1 a, di/dt ? 450 a/s, v dd ? v ds , t j ? 150 c. d. 1.6 mm from case. product summary v ds (v) - 400 r ds(on) ( ? )v gs = - 10 v 7.0 q g (max.) (nc) 13 q gs (nc) 3.2 q gd (nc) 5.0 configuration single s g d p-channel mosfet dpak (to-252) ipak (to-251) g d s s d g d ordering information package dpak (to-252) dpak (to-252) d pak (to-252) dpak (to-252) ipak (to-251) lead (pb)-free and halogen-free sihfr9310-ge3 sihfr9310trl-ge3 sihfr9310t r-ge3 sihfr9310trr-ge3 sihfu9310-ge3 lead (pb)-free irfr9310pbf irfr9310trlpbf a irfr9310trpbf a irfr9310trrpbf a irfu9310pbf sihfr9310-e3 si hfr9310tl-e3 a sihfr9310t-e3 a sihfr9310tr-e3 a sihfu9310-e3 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds - 400 v gate-source voltage v gs 20 continuous drain current v gs at - 10 v t c = 25 c i d - 1.8 a t c = 100 c - 1.1 pulsed drain current a i dm - 7.2 linear dera ting factor 0.40 w/c single pulse avalanche energy b e as 92 mj repetitive avalanche current a i ar - 1.8 a repetitive avalanche energy a e ar 5.0 mj maximum power dissipation t c = 25 c p d 50 w peak diode recovery dv/dt c dv/dt - 24 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (peak temperature) d for 10 s 300
irfr9310, irfu9310, sihfr9310, sihfu9310 www.vishay.com vishay siliconix s13-0166-rev. d, 04-feb-13 2 document number: 91284 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note a. when mounted on 1" square pcb (fr-4 or g- 10 material). notes a. repetitive rating; pu lse width limited by maximum junction temperature (see fig. 11). b. pulse width ? 300 s; duty cycle ? 2 %. c. this is applied for ipak, l s of dpak is measured between lead and center of die contact. thermal resistance ratings parameter symbol min. typ. max. unit maximum junction-to-ambient r thja - - 110 c/w maximum junction-to-ambient (pcb mount) a r thja --50 maximum junction-to-case (drain) r thjc --2.5 specifications (t j = 25 c, unless otherwise noted) parameter symbol test condi tions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = - 250 a - 400 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = - 1 ma - - 0.41 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = - 250 a - 2.0 - - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = - 400 v, v gs = 0 v - - - 100 a v ds = - 320 v, v gs = 0 v, t j = 125 c - - - 500 drain-source on-state resistance r ds(on) v gs = - 10 v i d = - 1.1 a b --7.0 ? forward transconductance g fs v ds = - 50 v, i d = - 1.1 a 0.91 - - s dynamic input capacitance c iss v gs = 0 v, v ds = - 25 v, f = 1.0 mhz, see fig. 5 - 270 - pf output capacitance c oss -50- reverse transfer capacitance c rss -8.0- total gate charge q g v gs = - 10 v i d = - 1.1 a, v ds = - 320 v, see fig. 6 and 13 b --13 nc gate-source charge q gs --3.2 gate-drain charge q gd --5.0 turn-on delay time t d(on) v dd = - 200 v, i d = - 1.1 a, r g = 21 ? , r d = 180 ? , see fig. 10 b -11- ns rise time t r -10- turn-off delay time t d(off) -25- fall time t f -24- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact c -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-dra in diode current i s mosfet symbol showing the integral reverse p - n junction diode --- 1.9 a pulsed diode forward current a i sm --- 7.6 body diode voltage v sd t j = 25 c, i s = - 1.1 a, v gs = 0 v b --- 4.0v body diode reverse recovery time t rr t j = 25 c, i f = -1.1 a, di/dt = 100 a/s b - 170 260 ns body diode reverse recovery charge q rr - 640 960 nc forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s and l d ) d s g s d g
irfr9310, irfu9310, sihfr9310, sihfu9310 www.vishay.com vishay siliconix s13-0166-rev. d, 04-feb-13 3 document number: 91284 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature 0.1 1 10 1 10 100 20s pulse width t = 25 c j top bottom vgs -15v -10v -8.0v -7.0v -6.0v -5.5v -5.0v -4.5v -v , drain-to-source voltage (v) -i , drain-to-source current (a) ds d -4.5v 0.1 1 10 1 10 100 20s pulse width t = 150 c j top bottom vgs -15v -10v -8.0v -7.0v -6.0v -5.5v -5.0v -4.5v -v , drain-to-source voltage (v) -i , drain-to-source current (a) ds d -4.5v 0.1 1 10 4 5 6 7 8 9 10 v = -50v 20s pulse width ds -v , gate-to-source voltage (v) -i , drain-to-source current (a) gs d t = 25 c j t = 150 c j -60 -40 -20 0 20 40 60 80 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 t , junction temperature ( c) r , drain-to-source on resistance (normalized) j ds(on) v = i = gs d -10v -1.8a
irfr9310, irfu9310, sihfr9310, sihfu9310 www.vishay.com vishay siliconix s13-0166-rev. d, 04-feb-13 4 document number: 91284 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area 1 10 100 0 100 200 300 400 500 -v , drain-to-source voltage (v) c, capacitance (pf) ds v c c c = = = = 0v, c c c f = 1mhz + c + c c shorted gs iss gs gd , ds rss gd oss ds gd c iss c oss c rss 0 4 8 12 16 0 4 8 12 16 20 q , total gate charge (nc) -v , gate-to-source voltage (v) g gs for test circuit see figure i = d 13 -1.1a v = -80v ds v = -200v ds v = -320v ds 0.1 1 10 1.0 2.0 3.0 4.0 5.0 -v ,source-to-drain voltage (v) -i , reverse drain current (a) sd sd v = 0 v gs t = 25 c j t = 150 c j 0.1 1 10 100 10 100 1000 operation in this area limited by r ds(on) single pulse t t = 150 c = 25 c j c -v , drain-to-source voltage (v) -i , drain current (a) i , drain current (a) ds d 10us 100us 1ms 10ms
irfr9310, irfu9310, sihfr9310, sihfu9310 www.vishay.com vishay siliconix s13-0166-rev. d, 04-feb-13 5 document number: 91284 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 9 - maximum drain curre nt vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case 25 50 75 100 125 150 0.0 0.4 0.8 1.2 1.6 2.0 t , case temperature ( c) -i , drain current (a) c d pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. - 10 v + - v ds v dd v gs 10 % 90 % v ds t d(on) t r t d(off) t f 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response)
irfr9310, irfu9310, sihfr9310, sihfu9310 www.vishay.com vishay siliconix s13-0166-rev. d, 04-feb-13 6 document number: 91284 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit a r g i as 0.01 t p d.u.t. l v ds + - v dd - 20 v driver 15 v i as v ds t p 25 50 75 100 125 150 0 50 100 150 200 250 300 starting t , junction temperature ( c) e , single pulse avalanche energy (mj) j as i d top bottom -0.49a -0.7a -1.1a q gs q gd q g v g charge - 10 v d.u.t. - 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
irfr9310, irfu9310, sihfr9310, sihfu9310 www.vishay.com vishay siliconix s13-0166-rev. d, 04-feb-13 7 document number: 91284 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 14 - for p-channel vishay siliconix maintains worldwide manufactu ring capability. products may be manufact ured at one of seve ral qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91284 . p.w. period di/dt diode recovery dv/dt body diode forward drop body diode forward current driver gate drive inductor current d = p.w. period + - - - - + + + peak dio d e recovery d v/ d t test circuit ? dv/dt controlled by r g ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low stray inductance ? g round plane ? low leakage inductance current tran s former r g ? compliment n-channel of d.u.t. for driver v dd ? i s d controlled by duty factor d note note a. v gs = - 5 v for logic level and - 3 v drive device s v gs = - 10 v a d.u.t. l s d waveform d.u.t. v d s waveform v dd re-applied voltage ripple 5 % i s d rever s e recovery current
package information www.vishay.com vishay siliconix revision: 16-may-16 1 document number: 71197 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 to-252aa case outline notes ? dimension l3 is for reference only. l3 d l4 l5 b b2 e1 e1 d1 c a1 gage plane height (0.5 mm) e b3 e c2 a l h millimeters inches dim. min. max. min. max. a 2.18 2.38 0.086 0.094 a1 - 0.127 - 0.005 b 0.64 0.88 0.025 0.035 b2 0.76 1.14 0.030 0.045 b3 4.95 5.46 0.195 0.215 c 0.46 0.61 0.018 0.024 c2 0.46 0.89 0.018 0.035 d 5.97 6.22 0.235 0.245 d1 4.10 - 0.161 - e 6.35 6.73 0.250 0.265 e1 4.32 - 0.170 - h 9.40 10.41 0.370 0.410 e 2.28 bsc 0.090 bsc e1 4.56 bsc 0.180 bsc l 1.40 1.78 0.055 0.070 l3 0.89 1.27 0.035 0.050 l4 - 1.02 - 0.040 l5 1.01 1.52 0.040 0.060 ecn: t16-0236-rev. p, 16-may-16 ? dwg: 5347
document number: 91362 www.vishay.com revision: 15-sep-08 1 package information vishay siliconix to-251aa (high voltage) notes 1. dimensioning and toler ancing per asme y14.5m-1994. 2. dimension are shown in inches and millimeters. 3. dimension d and e do not include mold flash. mold flash s hall not exceed 0.13 mm (0.005") per side. these dimensions are mea sured at the outermost extremes of the plastic body. 4. thermal pad contour optional with dimensions b4, l2, e1 and d1. 5. lead dimension uncontrolled in l3. 6. dimension b1, b3 and c1 apply to base metal only. 7. outline conforms to jedec outline to-251aa. base metal plating b 1, b 3 ( b , b 2) c1 (c) section b - b and c - c d a c2 c lead tip 5 5 (dat u m a) thermal pad e1 4 d1 v ie w a - a a1 a a c seating plane c c b b 1 2 b 4 4 4 3 5 l1 l l3 3 x b 2 3 x b 3 b 4 e 2 x e 0.010 c b m a 0.25 0.010 b a 0.25 l2 a c m millimeters inches millimeters inches dim. min. max. min. max. dim. min. max. min. max. a 2.18 2.39 0.086 0.094 d1 5.21 - 0.205 - a1 0.89 1.14 0.035 0.045 e 6.35 6.73 0.250 0.265 b 0.64 0.89 0.025 0.035 e1 4.32 - 0.170 - b1 0.65 0.79 0.026 0.031 e 2.29 bsc 2.29 bsc b2 0.76 1.14 0.030 0.045 l 8.89 9.65 0.350 0.380 b3 0.76 1.04 0.030 0.041 l1 1.91 2.29 0.075 0.090 b4 4.95 5.46 0.195 0.215 l2 0.89 1.27 0.035 0.050 c 0.46 0.61 0.018 0.024 l3 1.14 1.52 0.045 0.060 c1 0.41 0.56 0.016 0.022 1 0' 15' 0' 15' c2 0.46 0.86 0.018 0.034 2 25' 35' 25' 35' d 5.97 6.22 0.235 0.245 ecn: s-82111-rev. a, 15-sep-08 dwg: 5968
application note 826 vishay siliconix document number: 72594 www.vishay.com revision: 21-jan-08 3 application note recommended minimum pads for dpak (to-252) 0.420 (10.668) recommended mi nimum pads dimensions in inches/(mm) 0.224 (5.690) 0.180 (4.572) 0.055 (1.397) 0.243 (6.180) 0.087 (2.202) 0.090 (2.286) return to index return to index
legal disclaimer notice www.vishay.com vishay revision: 08-feb-17 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners. ? 2017 vishay intertechnology, inc. all rights reserved

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